An Integrated Circuit (IC) is an electronic circuit whose components are directly manufactured into a substrate of semiconductor material. The substrates of the great majority of the presently available ICs are obtained from wafers of silicon (Si).
Silicon wafers are usually formed of highly pure, monocrystalline silicon. A well-known manufacturing process for generating wafers of this type is the so-called “Czochralski growth process”. More in detail, a seed crystal of silicon is introduced into a mass of melted silicon. Then, the seed is gradually pulled out from the melted silicon, while being slowly rotated. In this way, the amount of melted silicon collected by the seed cools off, forming a cylindrical ingot. The crystalline orientation of the resulting ingot is determined by the seed crystal. The ingot is then sliced with a saw (e.g., a wire saw) and polished to form wafers. In this way, it is possible to obtain silicon wafers in a variety of sizes, e.g., having diameters ranging from 25.4 mm (1 inch) to 300 mm (11.8 inches). ICs for power applications are typically manufactured on wafers having diameters of 6-8 inches.
Silicon carbide (SiC) wafers have been recently developed. Compared to silicon, SiC has different physical properties, at least partly due to the fact that SiC is a semiconductor having a wider energy bandgap than Silicon. The following table shows the values of the energy bandgap (Eg), the breakdown electric field (Ec), and the electron mobility (μ) of Silicon and SiC, respectively:
Silicon (Si)Silicon Carbide (SiC)Eg1.1eV3eVEc30V/μm300V/μmμ[[M]]400cm2/Vsec40cm2/Vsec
From the above table it can be observed that SiC has a higher breakdown electric field Ec. Therefore, SiC is a material that may be advantageously used for manufacturing electronic circuits for power applications, since a wafer (and, thus, an IC substrate) made in SiC is able to sustain relatively high voltages even with a relatively small thickness.
SiC wafers cannot be generated using the manufacturing process employed for forming silicon wafers, i.e., the Czochralski growth process. Indeed, SiC is a material that directly passes (sublimates) from the solid phase to the vapor phase, without passing through any liquid phase, the latter phase being instead required in the Czochralski growth process for forming the melting wherein the seed crystal is introduced.
A SiC wafer is usually produced starting from an already formed silicon wafer, and then by forming on a surface thereof a layer of SiC. The currently known methods for forming SiC wafers of this type are quite expensive, and do not guarantee high degrees of quality, especially from the crystal lattice point of view. More particularly, since the crystal lattice of silicon is different from that of SiC, the resulting SiC wafer is unavoidably subjected to a relatively pronounced warping (in jargon, “wafer bow”, or simply “bow”). If the bow exceeds a certain threshold, the SiC wafer should be discarded, since the subsequent steps for integrating electronic devices in the wafer typically require a sufficiently planar wafer. Moreover, the largest wafer diameter currently obtainable by the known processes is limited to about 4 inches, i.e., roughly half of the diameter typically required for power applications. Similar drawbacks occurs as well by considering wafers made in other semiconductor materials like Gallium Nitride (GaN).
The paper “Growth of Si/3C-SiC/Si(100) heterostructures by pulsed supersonic free jets” by Y. Ikoma, T. Endo, F. Watanabe, and T. Motooka, Applied Physics Letters, vol. 75, no. 25, 20 Dec. 1999, pages 3977-3979, which is incorporated by reference, discloses a method for the epitaxial growth of multilayer structures of Si/3C-SiC/Si(100) by pulsed supersonic free jets of methylsilane (CH3SiH3) for SiC growth and trisilane (Si3H8) for Si growth.
The paper “Ion beam synthesis of buried SiC layers in silicon: Basic physical processes” by Jörg K. N. Lindner, Nuclear Instruments and Methods in Physics Research, vol. 178, May 2001, pages 44-45, which is incorporated by reference, provides a review of the basic physical processes leading to a distribution of amorphous and crystalline phases during high-dose, high-temperature, carbon implantation into silicon.